The ED PLD Tool is a PLD fuse map editor with the capability to read, burn, verify, and test PLDs using the PLD burner on the Logic Engine Board. ED PLD supports only the Cypress PLD C 20G10 at this time.
6.2 Cypress PLD C 20G10
The 20G10 is a 24 pin PLD with 12 input pins and 10 I/O pins. Each of the 10 output cells can be configured as registered or combinational outputs, true high or true low outputs, and product term or pin 13 output enable signals. The registered outputs are clocked by input pin 1. The fuse matrix consists of 44 signals (12 input, 10 output feedbacks, and their compliments). Each output cell has 9 product terms, 1 output enable term and 8 terms feeding an OR-gate. The functional logic diagram of the PLD C 20G10 is shown in Fig. 1 and the eight possible configurations of the output cells are shown in Table 1 and Figs. 2-3. For more information on the PLD C 20G10, consult the data sheet.
Figure 17. Functional Logic Diagram of PLD C 20g10
Figure 18. Registered Output Configurations.
Figure 19. Combinational Output Configurations.Table IV. Configuration Table.
| Figure | C2 | C1 | C0 | Configuration |
|---|---|---|---|---|
| 2A | 0 | 0 | 0 | Product Term OE Registered Active LOW |
| 2B | 0 | 0 | 1 | Product Term OE Registered Active HIGH |
| 3A | 0 | 1 | 0 | Product Term OE Combinational Active LOW |
| 3B | 0 | 1 | 1 | Product Term OE Combinational Active HIGH |
| 2C | 1 | 0 | 0 | Pin 13 OE Registered Active LOW |
| 2D | 1 | 0 | 1 | Pin 13 OE Registered Active HIGH |
| 3C | 1 | 1 | 0 | Pin 13 OE Combinational Active LOW |
| 3D | 1 | 1 | 1 | Pin 13 OE Combinational Active HIGH |
6.3 EDPLD Fuse Map Editor
As a fuse map editor, the EDPLD tool provides an easy and integrated way to generate a file in the proper format for the PLD programmer. The files generated by the editor are simple ASCII files that conform to a specific format (see section 6.6). These files can of course be generated and edited by any text editor. The EDPLD editor will however, ensure that the file is generated in the proper format.
When the ED PLD tools is started, a window such as that shown in Fig. 4 is opened. This window represents a view of one output cell of a 20G10 and its fuse matrix. The window consist of four sections: a menu bar across the top, fuse matrix fields through the middle, output configuration fields on the right, and two scroll fields on the bottom right.
Figure 20. The ED PLD Window
The fuse matrix fields are arranged in 9 rows. One for the output enable signal (labeled OE) and eight for the product terms (labeled 0-7). Each row contains 22 fuse matrix fields organized in pairs of two. Each of the fuse matrix fields represents one signal of the 12 input and 10 feedback signals. Each column is labeled with the pin number of the signal it represents. The fuse matrix fields consist of two characters representing the two polarities of the signal. Each character can be either a '.' indicating the absence of a fuse or a 'x' indicating the presence of a fuse. For the input signals the true high signal comes first followed by the true low signal. For the output feedback signals the order of the signals depends on the configuration of the output cell. Refer to Figs 1-3 to determine the proper orientation.
The fuse matrix fields can be in one of four configurations. When selected, the configuration of the field will advance to the next configuration in the sequence ('..' '.x' 'x.' 'xx' '..').
The output configuration fields can each be in one of two states. When selected, the fields will toggle states. Besides a ',' or a 'x' being displayed in each field, a mnemonic is displayed in each field indicating the current configuration.
The two scroll fields are used to move the view to the next or previous output cell. The pin number of the current output cell is displayed above the scroll fields. The Page Up and Page Down keys can also be used for this function.
6.4 File I/O
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 23
0 OE x... .... .... .... .... .... .... .... .... .... ....
0 0 .... x... .... x... .x.. .x.. .x.. .x.. .xx. .x.. .x.x . H
0 1 .... x... .... x... .x.. .x.. .x.. .x.. .x.. .xx. .x.x . C
0 2 .... .x.. x... .... .... .... .... .... .... .... .... x P
0 3 .... .x.. x... .... .... .... .... .... .... .... ....
0 4 .... .x.. x... .... .... .... .... .... .... .... ....
0 5 .... .x.. x... .... .... .... .... .... .... .... ....
0 6 .... .x.. x... .... .... .... .... .... .... .... ....
0 7 .... .x.. x... .... .... .... .... .... .... .... ....
Figure21. Example of Configuration Block 0
The ED PLD software has several functions used to save and retrieve fuse maps. Save File - saves the current fuse map into the current file. If there is no current file, the user is prompted for a file name. Save File As - saves the current fuse map into the named file and Load File -loads the named file into the editor. Initially the current file is undefined. Each time a file is named, using any of these functions, that file becomes the current file and will be displayed as the title of the ED PLD window.
The files created by the ED PLD editor, called fuse map files, have a specific format. These files are text files and can be edited using other text editors, but they must conform to the fuse map format described below.
Each fuse map file consists of 10 configuration blocks which describe the product terms and architecture of each output cell. Fig. 5 is an example of one configuration block and Fig. 6 is an example of a complete fuse map file.
Each configuration block consists of exactly 10 lines. The first line is a comment that typically contains the pin numbers corresponding to each column of the product terms and the pin number of the output cell. The second line contains the product term for the output enable signal. The following 8 lines contain the product terms which feed the OR-gate of the output cell. Each of the product term lines must contain in the first column, the number of the configuration block (0-9). The product term for the output enable signal must contain the letters 'OE' in the third and fourth column. The remaining 8 product terms must contain in the fourth column, the number of the product term (0-7).
Starting in column 5, each product term line contains a fuse pattern consisting of 44 fuse bits. These are typically arranged in 11 groups of 4 bits separated by a space, however, spaces can occur throughout the line and are ignored. In addition, product terms 0, 1, and 2 contain an extra fuse bit beyond the 44 fuse bits which configure the architecture of the output cell. Each fuse bit is either a `.' or a `x'. A `.' indicates the absence of a fuse and a `x' indicates the presence of a fuse. Any characters beyond the fuse bits are considered comments and are ignored.
The product terms are arranged as a sequence of pairs of fuse bits, one pair for each input signal and output feedback signal. One fuse bit of each pair is for the true high and the other is for the true low version of the signal. For the input signals the true high signal comes first followed by the true low signal. For the output feedback signals the order of the signals depends on the configuration of the output cell. Refer to Figs 1-3 to determine the proper orientation.
The three fuse bits beyond product terms 0, 1, and 2 (referred to as C0, C1, and C2) configure the architecture of the output cell. Each fuse bit controls one aspect of the configuration as described below:
| C0 . | : True High (H) |
| x | : True Low (L) |
| C1 . | : Combinational Output (C) |
| x | : Registered Output (R) |
| C2 . | : Output Enable source is pin 13 (C) |
| x | : Output Enable source is product term (P) |
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 23
0 OE x... .... .... .... .... .... .... .... .... .... ....
0 0 .... x... .... x... .x.. .x.. .x.. .x.. .xx. .x.. .x.x . H
0 1 .... x... .... x... .x.. .x.. .x.. .x.. .x.. .xx. .x.x . C
0 2 .... .x.. x... .... .... .... .... .... .... .... .... x P
0 3 .... .x.. x... .... .... .... .... .... .... .... ....
0 4 .... .x.. x... .... .... .... .... .... .... .... ....
0 5 .... .x.. x... .... .... .... .... .... .... .... ....
0 6 .... .x.. x... .... .... .... .... .... .... .... ....
0 7 .... .x.. x... .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 22
1 OE x... .... .... .... .... .... .... .... .... .... ....
1 0 .... x... .... x... .x.. .x.. .x.. .x.. .xx. .x.. .x.x . H
1 1 .... x... .... x... .x.. .x.. .x.. .x.. .x.. .xx. .x.x . C
1 2 .... .x.. x... .... .... .... .... .... .... .... .... x P
1 3 .... .x.. x... .... .... .... .... .... .... .... ....
1 4 .... .x.. x... .... .... .... .... .... .... .... ....
1 5 .... .x.. x... .... .... .... .... .... .... .... ....
1 6 .... .x.. x... .... .... .... .... .... .... .... ....
1 7 .... .x.. x... .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 21
2 OE x... .... .... .... .... .... .... .... .... .... ....
2 0 .... x... .... x... .x.. .x.. .x.. .x.. .x.. .x.. .xx. . H
2 1 .... .x.. .x.. .... .... .... .... .... .... .... .... . C
2 2 .... .x.. .x.. .... .... .... .... .... .... .... .... x P
2 3 .... .x.. .x.. .... .... .... .... .... .... .... ....
2 4 .... .x.. .x.. .... .... .... .... .... .... .... ....
2 5 .... .x.. .x.. .... .... .... .... .... .... .... ....
2 6 .... .x.. .x.. .... .... .... .... .... .... .... ....
2 7 .... .x.. .x.. .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 20
3 OE x... .... .... .... .... .... .... .... .... .... ....
3 0 .... x... .... x... .x.. .x.. .... .x.. ..x. .... ...x . H
3 1 .... x... .... x... .x.. .x.. .... .x.. .... ..x. ...x . C
3 2 .... x... .... x... .x.. .x.. .... .x.. .... .... x... x P
3 3 .... x... .... x... .x.. .x.. .... .x.. .... x... ....
3 4 .... x... .... x... .x.. .x.. .... .x.. x... .... ....
3 5 .... x... .... x... .x.. .x.. x... .... .... .... ....
3 6 .... x... .... x... .x.. .x.. x... .... .... .... ....
3 7 .... x... .... x... .x.. .x.. x... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 19
4 OE x... .... .... .... .... .... .... .... .... .... ....
4 0 .... .... .... x... .x.. .... .x.. .... .xx. ...x ...x . H
4 1 .... .... .... x... .x.. .... .x.. .... .x.. .... x... . C
4 2 .... .... .... x... .x.. .... .x.. .... .x.. x... .... x P
4 3 .... .... .... x... .x.. .... .x.. x... .... .... ....
4 4 .... .... .... x... .x.. x... .... .... .... .... ....
4 5 .... .x.. .... .... .... .... .... .... .... .... ....
4 6 .... .x.. .... .... .... .... .... .... .... .... ....
4 7 .... .x.. .... .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 18
5 OE x... .... .... .... .... .... .... .... .... .... ....
5 0 .... x... .... x... .... .x.. .x.. .... .... .x.. x... . H
5 1 .... x... .... x... .... .x.. .x.. .... x... .... .... . C
5 2 .... x... .... x... .... .x.. .x.. x... .... .... .... x P
5 3 .... x... .... x... x... .... .... .... .... .... ....
5 4 .... x... .... x... x... .... .... .... .... .... ....
5 5 .... x... .... x... x... .... .... .... .... .... ....
5 6 .... x... .... x... x... .... .... .... .... .... ....
5 7 .... x... .... x... x... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 17
6 OE .... .... .... .... .... .... .... .... .... .... ....
6 0 ..xx .... .... .... .... .... .... .... .... .... .... . H
6 1 ..xx .... .... .... .... .... .... .... .... .... .... . C
6 2 ..xx .... .... .... .... .... .... .... .... .... .... x P
6 3 ..xx .... .... .... .... .... .... .... .... .... ....
6 4 ..xx .... .... .... .... .... .... .... .... .... ....
6 5 ..xx .... .... .... .... .... .... .... .... .... ....
6 6 ..xx .... .... .... .... .... .... .... .... .... ....
6 7 ..xx .... .... .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 16
7 OE .... .... .... .... .... .... .... .... .... .... ....
7 0 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x x L
7 1 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x . C
7 2 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x x P
7 3 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x
7 4 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x
7 5 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x
7 6 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x
7 7 .... .... .... .... .x.. .x.. .x.. .x.. .x.x .x.x .x.x
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 15
8 OE ..xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
8 0 .... .... .... .... .... .... .... .... .... .... .... . H
8 1 .... .... .... .... .... .... .... .... .... .... .... . C
8 2 .... .... .... .... .... .... .... .... .... .... .... x P
8 3 .... .... .... .... .... .... .... .... .... .... ....
8 4 .... .... .... .... .... .... .... .... .... .... ....
8 5 .... .... .... .... .... .... .... .... .... .... ....
8 6 .... .... .... .... .... .... .... .... .... .... ....
8 7 .... .... .... .... .... .... .... .... .... .... ....
1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 1014 1113 PIN 14
9 OE ..xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
9 0 .... .... .... .... .... .... .... .... .... .... .... . H
9 1 .... .... .... .... .... .... .... .... .... .... .... . C
9 2 .... .... .... .... .... .... .... .... .... .... .... x P
9 3 .... .... .... .... .... .... .... .... .... .... ....
9 4 .... .... .... .... .... .... .... .... .... .... ....
9 5 .... .... .... .... .... .... .... .... .... .... ....
9 6 .... .... .... .... .... .... .... .... .... .... ....
9 7 .... .... .... .... .... .... .... .... .... .... ....
Figure 22. Example Fuse Map File
Beyond each of these three fuse bits there is typically a single character comment indicating the configuration of the output cell. These characters are given above in parenthesis.
Although the fuse map file format is rigid, creating and editing a fuse map file is quite easy. To create a new file, simply enter the pld program and select option 2 (Save buffer) and specify a filename. This will save the initial empty buffer into the named file. To edit an existing fuse map file, use your favorite text editor in overstrike mode to alter the fuse bits.
6.5 EDPLD PLD Programmer
There are several functions available in the ED PLD editor for testing, programming, and verifying a 20G10 in the programmer socket on the Logic Engine Board. These functions are all available under the Pld menu and are described below in section 6.7. Each of these functions will prompt the user to insert a 20G10 into the programmer socket. The programmer socket is the zero insertion force socket located near the center of the Logic Engine board below the bank of leds. The 20G10 should be oriented in the socket so that pin 1 is on the left (the same orientation as the other chips on the board.) The lever on the socket should be in the up position when inserting or removing a chip and in the down position to lock a chip into the socket. It is important that the 20G10 not be inserted until the prompt appears and at not time should a 20G10 be inserted or removed when one of the leds surrounding the programmer socket is on. After the 20G10 is inserted, hit any key to proceed with the operation. Some of the functions will display dialog boxes indicating the sucess or failure of the operation. Hit any key to remove one of these messages. The Test Device function is a little more involved and is described in the next section.
6.6 Testing a 20G10
The EDPLD tool has the ability to apply a set of test vectors to a 20G10 in the programmer socket and read the outputs of the 20G10. When the Test Device function is selected, the user will first be prompted to supply the file name of a test vector file. The format of a test vector file is described below. After supplying the file name, the user is prompted to insert the 20G10 into the programming socket. After the 20G10 is inserted, hit any key to begin the testing of the device. After the device has been tested, a window will be displayed showing the results of the test. This window can be scrolled using the cursor keys. The window can only display up to fifty lines of information. If the information is longer than fifty lines, it will be truncated and a message will be displayed at the bottom of the window so indicating. This window can be closed by hitting the ESC key. After the window is closed, a dialog box will be displayed indicating the number of errors that occured during testing.
The output of the testing can also be logged to a file. This can be done by use of the Log File function under the file menu. This function will prompt the user for the name of the log file. All subsequent output from testing will be sent to this file and no window will be displayed containing this information. Also, the information being sent to the log file will not be truncated.
Each test vector consists of a line of 24 characters, one for each pin of the device, in order from pin 1 to pin 24. Any number of test vectors can occur in a file, one per line. A blank line or a line starting with a `#' or a ` ' (space) is considered a comment and ignored. The valid characters for each type of pin are given below:
| Input Pins: 1-11,13 | |
|---|---|
| 1 | Apply 5V |
| 0 | Apply 0V |
| C | Clock (0V-5V-0V) |
| K | Clock (5V-0V-5V) |
| N | This pin is not tested |
| Input/Output Pins: 14-23 | |
| 1 | Apply 5V (assumes pin is configured as an input) |
| 0 | Apply 0V (assumes pin is configured as an input) |
| C | Clock (0V-5V-0V) (assumes pin is configured as an input) |
| K | Clock (5V-0V-5V) (assumes pin is configured as an input) |
| H | Expected result is 5V (assumes pin is configured as an output) |
| L | Expected result is 0V (assumes pin is configured as an output) |
| Z | Expected result is High Z |
| I | Expected result is opposite of High Z (i.e when the pin is pulled high, its value is low and when it is pulled low its value is high). It is not exepected that this will be used in a test vector, but it does show up in the output of the test. This usually occurs when the pin is not being tested and it depends on other pins that are also not being tested. |
| N | This pin is not tested |
| Power Pins: 12,24 | |
| N | This pin is not tested |
After a file has been created containing the desired test vectors, they can be applied to the device under test as described above. After testing each vector will be displayed. If there is an error in the format of the test vector, an error message will be displayed and the test vector will be skipped. If there is an error in the expected results, the actual results will be displayed along with an error message indicating the location of the error. After all the test vectors have been applied, a message will be displayed indicating the total number of errors which occurred. Below is an example set of test vectors followed by an example output from running the set of test vectors:
Test Vectors: 10000010000N0NNNNNNNNNHN 10000001000N0NNNNNNNNNHN 10000000100N0NNNNNNNNNHN 10000000000N0NNNNpNNNNLN 01111111111N1NNNNHHNNNZN Output: VECTOR: 10000010000N0NNNNNNNNNHN : Passed VECTOR: 10000001000N0NNNNNNNNNHN : Passed VECTOR: 10000000100N0NNNNNNNNNHN : Passed ERROR: Illegal character in vector: p VECTOR: 10000000000N0NNNNpNNNNLN : Skipped VECTOR: 01111111111N1NNNNHHNNNZN : Failed RESULTS: 01111111111N1ZZZZZLLLZZN ERRORS: ^^ Test Completed with 3 Errors
6.7 Key Bindings
| Key stroke | Menu | Description |
|---|---|---|
| F1 | - | Activate File menu. |
| F2 | - | Activate Display menu. |
| F3 | - | Activate Pld menu. |
| F4 | - | Activate Tools menu. |
| F12 | - | Activate Help menu. |
| F5 | File | Load File: Load a fuse map file into the buffer. The user is prompted for the file name. This file becomes the current file. |
| F6 | File | Save File: Save the current buffer into the current file. If there is no current file the user is prompted for the file name. |
| A-F6 | File | Save File As: Save the current buffer into the named file. |
| F7 | File | Log File: Name the file for logging output from the application of test vectors. |
| ESC | File | Exit. |
| Page Down | Display | Next Block: Move view to the next output cell. |
| Page Up | Display | Previous Block: Move view to the previous output cell. |
| DEL | Display | Clear Block: Set all fuses for this output cell to '.' (absence of a fuse). |
| A-B | Pld | Blank Test: Test for a blank device in the PLD Burner socket. The user is prompted to insert the device in the socket at the proper time. |
| A-P | Pld | Program Device: Program the device in the PLD Programmer socket with the contents of the buffer. The user is prompted to insert the device at the proper time. If the device is not blank, the user is prompted whether to continue. |
| A-R | Pld | Read Device: Read the contents of the device in the PLD Programmer socket into the buffer. The user is prompted to insert the device in the socket at the proper time. |
| A-V | Pld | Verify Device: Read the contents of the device in the PLD Programmer socket and compare it to the contents of the buffer. The number of differences between the two is displayed. The user is prompted to insert the device in the socket at the proper time. |
| A-T | Pld | Test Device: Apply a set of test vectors to the device in the PLD Programmer socket. The user is prompted to insert the device in the socket and for the name of the file containing the test vectors. |
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