STAR TDC DOCUMENTS

EMC TDC I/O


TDC reference
  • TDC VME interface & programming 5/21/01

  • Download-able Xilinx FPGA hex files
  • INRX.HEX 5/31/01
  • IMUX.HEX 11/17/00
  • SCORE.HEX 6/18/01
  • SCOREP.HEX 9/6/01 DAQ busy mod & L0trig 4 7 8 9
  • SCOREP.HEX 8/25/02 DAQ busy bug fix
  • SCOREP.HEX 12/28/02 Input Card token number broadcast fix
  • SCOREP.HEX 1/19/03 Clock DLL reset fix
  • SCOREP.HEX 3/27/03 RHIC Storbe rising edge detect (for non 1/5 RHICSTRB)
  • GLMUX.HEX 5/31/01
  • GLMUXR.HEX 192 ADC channel version 10/27/03
  • GLMUXS.HEX 1 input card version 10/27/03

  • tdci4008.hex 5/31/01
  • tdcx4008.hex 11/17/00

  • Debuging Code in Scheme
  • TDCFPGA4.SS 2/28/01
  • TDCFPGA5.SS 5/18/01
  • TDCINRX7.SS 5/11/01

  • EMC transmission protocols to/from TDC
  • HOTLink from FEE to TDC 10/4/99
  • GLink from TDC to DAQ and L2 4/28/00


  • EMC TDC internal

  • TDC command bus descripton 11/2/00
  • tdc0v1 5/21/01
  • tdc1v1 5/21/01
  • tdc11v1 5/21/01
  • tdc12
  • tdc13
  • tdc13n
  • tdc2
  • tdc21daq
  • tdc21l2
  • tdc22
  • tdc23
  • tdc3
  • tdcpc.pdf


  • Input Card Schematic
  • i1
  • i2
  • i3
  • i4
  • i5
  • i6
  • i7
  • i8
  • i9
  • i10
  • i11
  • i12

  • Output Card Scehmatic
  • o1
  • o2
  • o3
  • o4
  • o5
  • o6
  • o7
  • o8
  • o9
  • o10
  • o11
  • o12
  • o13
  • o14
  • o15
  • o16