Assignment I (Verilog)

Write Verilog programs to implement the following circuits. Simulate each circuit independently. Based on your experience, write a one paragraph analysis of the suitability of simulation as a verification method.

• Implement a behavioral description of a half-adder. A half-adder is a circuit that takes two one-bit inputs: x and y, and produces two one-bit outputs: a sum and a carry.
• Use the implementation of the half-adder to define a structural description of a full adder. A full adder takes three inputs: two bits and a previous carry and produces two outputs: a carry bit and a sum bit.
• Use the implementation of the full-adder to define a parallel 4-bit ripple carry adder. What if I wanted a 128-bit adder?
• Now add 1-unit delays to all operations. Show a bogus simulation case where the result of the 4-bit addition does not have time to settle. What is the maximum rate at which we can do additions in this case?

You will need the Veriwell simulator:

• setenv PATH /local/apps/veriwell/bin:$PATH
• setenv VERIWELL_RPATH '/local/apps/veriwell/bin'
• to run text version of simulator: veriwell mainfile file1 ...
• to run the GUI version: mveriwell (does not work on some machines for reasons I don't know)

If you use emacs, copy this file somewhere in your load path: verilog-mode.el, and then add this somewhere where it can be loaded:

(autoload 'verilog-mode "verilog-mode" nil t)

(setq auto-mode-alist (append (list (cons "\\.v$" 'verilog-mode)
				    (cons "\\.f$" 'verilog-mode))
			      auto-mode-alist))

(setq verilog-mode-hook '(lambda ()
			   ;; User specifications
			   (setq verilog-tab-always-indent t
				 verilog-auto-newline nil
				 verilog-auto-endcomments t
				 verilog-indent-level 3
				 verilog-continued-expr 1
				 verilog-label-offset -2
				 verilog-case-offset 2
				 )))