Consider the following subset of Verilog called V0 (from Mike Gordon's notes)
Programs P ::= always S Statements S ::= x = exp Blocking assignment | x <= exp Non-blocking assignment | begin {:label} S; ...; S end Blocks | disable label Jumps | if (exp) S {else S} Conditionals | while (exp) S Loops | forever S Infinite Loops | @ S Timing ControlYour job is to write a synthesizer for that language that produces programs of the following form:
Programs P ::= forever C Commands C ::= x1 := E1, x2 := E2, ... Expressions E ::= usual expressions | E -> E1 | E2For example, the source program:
always begin @ x = 3; @ y = x + 4; endcompiles to:
forever pc := (pc=0 -> 1 | pc=1 -> 0); x := (pc=0 -> 3 | pc=1 -> x); y := (pc=0 -> y | pc=1 -> x+4);In case you don't have a working parser, here are my v0.lex and v0.cup files.
sabry@cs.uoregon.edu