Hardware/Software Interface

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# 181U Spring 2020
### Software/Hardware Interface

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- Geoffrey Brown, 2020
- 181U
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# Agenda

* Memory Mapped I/O
* Interrupts
* DMA

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# Memory Mapped Input/Output (I/O)

* Signals and Timing Diagrams
* Functions and Latches
* General Purpose I/O

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# Bus Model of Processor

![](images/2019-12-27-13-05-44.png# w-60pct fr)

* CPU (central processing unit) communicates with memory and I/O devices over a bus.
* Everything on the bus looks like memory to the CPU
* A bus consists of a set of *shared* signal wires -- Address wires, Data wires, and Control wires.
* Communication over bus is time dependent

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# Memory Operations

At the machine instruction level, this interface is completely hidden.  The Cortex-M (and most processors)
has two basic memory access instructions.  Load, which reads from "memory" with an address(pointer)

```asm
ldr r1, [r2]     @   r1 = *r2
```
and Store, which writes to a memory address

```asm 
ldr r1, [r2]     @  *r1 = r1
```
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# Cortex Address Map

![](images/2019-12-27-13-12-29.png# w-40pct fr)

The Cortex-M architecture reserves ranges of memory for specific functions --

* peripherals (hardware devices), 
* data (SRAM), 
* and code.

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# Aside on Timing Diagrams

![](images/space.png# w-2-12th)
![](images/2019-12-27-13-14-08.png# w-70pct)

* Timing diagrams provide a way to specify and reason about signals on a bus. 
* There are three electrical levels  -- high, low, floating
* There are two logical levels -- 1, 0
* We often describe groups of wires with hexadecimal or decoded values
* Wires can be *driven* in both directions, but not at the same time

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# Timing Diagram Example -- Memory Access

![](images/space.png# w-2-12th)
![](images/2019-12-27-13-17-15.png# w-70pct)

In this example there are three memory transactions
* Read from address 0x04 -- returns 1
* Write 2 to address 0x04
* Read from address 0x04 -- returns 1
Notice that the Data lines are allowed to float between transactions.
* On reads, the data lines are *driven* by the memory/device
* On writes, the data lines are *driven* by the cpu

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# Hardware primitives -- finite functions

![](images/space.png# w-20pct)
![](images/2019-12-27-13-22-31.png# w-60pct)

* In principle, we can build any function with finite input and outputs from boolean logic gates
* In practice, inputs and output signals are restricted to the processor word size (or less)
* In practice, only relatively simple operations are implemented in a single functions (e.g. add,and)..
)

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# Hardware primitives -- latch

![](images/space.png# w-20pct)
![](images/2019-12-27-13-25-29.png# w-60pct)

A *latch* provides a state-holding element.  
* We can build them in any width.  
* The basic operating is "load" which copies the input to the output
* When a load is not being performed, the output is preserved even if the input changes.

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# Hardware primitives -- buffer

![](images/space.png# w-20pct)
![](images/2019-12-27-13-27-45.png# w-60pct)

* A buffer provides a way to have multiple *drivers* on a bus
* The output of a buffer *floats* when it is not enabled
* When the buffer is enabled, its input is copied to its output

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# Example:  A single memory word

![](images/space.png# w-20pct)
![](images/2019-12-27-13-29-50.png# w-60pct)

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# Example:  Digital I/O Port

![](images/space.png# w-3-12th)
![](images/2019-12-27-13-31-26.png# w-50pct)

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# C Model of I/O Port

```C
typedef struct {
   volatile unsigned int in;
   volatile unsigned int out;
   volatile unsigned int dir;
} port;
```

```C
extern port *p;

p->dir = 3;    // set bits (pins) 0 and 1 to outputs
p->out = 1;    // set pin 0 to 1
x = p->in;     // read pins.
```

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# Interrupts

* Why Interrupts ?
* Basic interrupt processing
* Sources of interrupts
* Interrupt handlers

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# Polling

Suppose we are waiting for data from a communication device
* Polling is the process of querying the device (through software)
* Polling takes time away from other work
* Polling makes it difficult to satisfy real-time constraints

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# Interrupts

* **Interrupts** provide a general mechanism for hardware to signal the processor that attention is required
* Rather than repeatedly asking devices if they need service (polling) let the devices signal the processor.

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# The big idea

* For each type of event that potential needs service, associate a special procedure, called a **handler** that will be executed when the event occurs.
* We call these events *interrupts*
* In purely software implementations, **callbacks** serve the role of **handlers** -- this model is frequently used in GUIs
* Interrupt **handlers** are called by the CPU
    * Before each "normal" instruction is executed, the CPU checks for pending events
    * If an event is pending, the CPU transfers control to the associated handler.

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# Interrupt Service

![](images/space.png# w-20pct)
![](images/2019-12-27-13-47-41.png# w-60pct)

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# Instruction Execution with Interrupt Handling

![](images/space.png# w-10pct)
![](images/2019-12-27-13-48-54.png# w-80pct)

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# Key Points for Programmers

* If interrupts are **enabled**, they can occur at any point during program execution
* Interrupts are **disabled** when the handler is called (at least from the same priority level)
* Interrupt handlers are similar to normal procedures with a few caveats
    *  They must save *everything*, not just the regular callee saved registers
    *  They should not touch shared data except that specifically associated with the handler (e.g. an input queue)

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# The need to preserve registers (including status)

![](images/space.png# w-3-12th)
![](images/2019-12-27-13-53-37.png# w-50pct)

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# Revised Memory Layout

![](images/space.png# w-3-12th)
![](images/2019-12-27-13-55-02.png# w-50pct)

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# Sources of Interrupts

* External device **interrupts**
   * timer
   * Serial port
   * Button
* **Processor Exceptions** 
   * Memory access violation
   * Divide by zero
* **Software Interrupts**  -- OS system calls
    
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# Direct Memory Access (DMA)

* Example
* What DMA does
* STM32 DMA Architecture

```C
for (i = 0; i < N; i++) {
   while(flagBusy);
   buf[i] = peripheralRegister;
}
```

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# Performance Without DMA

![](images/2019-12-27-14-02-17.png)

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# Performance with DMA

![](images/2019-12-27-14-03-29.png)

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# How DMA works

![](images/space.png# w-10pct)
![](images/2019-12-27-14-09-08.png# w-80pct)

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# STM32 DMA Architecture

![](images/space.png# w-10pct)
![](images/2019-12-27-14-06-46.png# w-80pct)

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# Summary

* Memory Mapped I/O
* Interrupts
* Direct Memory Acces
* Cover (pxct): By <a href="https://de.wikipedia.org/wiki/User:Putput" class="extiw" title="de:User:Putput">Putput</a>, <a href="http://creativecommons.org/licenses/by-sa/3.0/" title="Creative Commons Attribution-Share Alike 3.0">CC BY-SA 3.0</a>, <a href="https://commons.wikimedia.org/w/index.php?curid=25662571">Link</a>