Computer Science Department , Indiana University

B441/B541 -- Digital Hardware Design Laboratory

Format of the Lab For the first nine weeks of the lab (except for the first lab), there will be an assignment due at the beginning of each lab. The assignment will typically consist of both written work and a working circuit on your logic engine. Since the PDP-8 is such a wiring intensive project, it will be divided into three parts with extended deadlines. In addition to the lab assignments, starting around mid-semester there will be weekly quizzes relating to the PDP-8.

Please note that, in general, you will be working in pairs. All written exercises are to be handed in individually and will be graded as individual work. You and your partner will co-operate on all circuits, however, and will be given a single grade for your circuitry. Because wiring experience will be shared, it is your responsibility to make sure you understand what wiring your partner has done and to make sure that you are doing your fair share. You may divide up the work however you and your partner prefer, but if we see that one of you is consistently not doing enough work, we may re-arrange the groups.

Assignment format Assignments will typically require you to turn in a drawing accompanied by a brief description of your design. The text should cover what the circuit does, how it does it, and why you chose to do it that way. Your drawings will have to be scaled to letter-sized paper, so do not use drawing formats larger than C size, as anything larger will be unreadable. 

Laboratory Grading

The lab grade will be broken down in the following way:

Lab Information

Laboratory Schedule
Digital Design B441/B541
Fall '03

NOTE: This is 2003's schedule. It is provided to give a general idea of objectives. The labs have changed for 2004 and the schedule is being revised. A new schedule will be posted as soon as it is ready.
Week Ending
Manual Section
Sep 5 Lab Demonstrations Physical Representation of Logic Values
Sep 12 Design Exercise Implementing Logic in Hardware / Xilinx Simulator
Sep 19 Lab 4, Lab 5.1 Programmable logic and FPGAs; 7-segment Decoder
Sep 26 Lab 5.2, Lab 6 Synthesis of combinatorial elements--muxes, comparators
Oct 3 Lab 7 Building an ALU
Oct 10 Lab 8 Counters and Sequential Logic
Oct 17 Lab 9/Lab 10 Register-transfer concepts; Building the PDP-8 data path
Oct 24 Lab 11 Completing the Data Path; Manual ASM control of the PDP-8
Oct 31 Lab 12 Building the PDP-8 controller: ASM state generator
Nov 7 Lab 12 Building the PDP-8 controller: ASM outputs
Nov 14 Lab 13 Debugging and testing your PDP-8 processor
Nov 21 Lab 14 Building your own UART and serial interface
Nov 28 --- (Thanksgiving break)
Dec 5 --- Debugging and testing your UART and serial interface
Dec 12 --- Final PDP-8 test and lab checkout
Dec 19 --- (Finals week -- no scheduled lab activity)